1. Field of the Invention
The present invention relates to the mounted state of solder for connecting a substrate to electrodes for external connection of a semiconductor device in a mounting structure and, in particular, relates to a chip size package (CSP) type semiconductor device wherein visual inspection can be carried out.
2. Description of the Related Art
Semiconductor elements separated from a wafer by means of dicing are secured to lead frames in an assembly process for a semiconductor device according to a conventional art. After that, the semiconductor elements are sealed in a transfer mold. Then, the lead frames and resin layer are cut into individual semiconductor devices. A semiconductor device obtained by such a process has, for example, a structure as shown in FIG. 6 wherein the outside of semiconductor element 1 is covered with a resin layer 2 and lead terminals 3 for external connection are led out from the sides of this resin layer 2. This structure is disclosed in, for example, Japanese Unexamined Patent Publication Hei-05-129473.
Thus, this structure has problems with the process precision of the lead frame and with the precision of positioning vis-à-vis dies due to the protrusion of lead terminals 3 out of resin layer 2. Therefore, there is a limitation to the scaling down of the external dimensions and of the area required for mounting the semiconductor device.
Recently, a wafer-scale CSP having outer dimensions that can be scaled down to dimensions equal to, or very close to, the size of a semiconductor chip has attracted attention. In order to manufacture the above, first, a large number of semiconductor elements 12 are formed by carrying out pre-processing such as diffusion of a variety of types to a semiconductor wafer 11, as shown in FIG. 7(A). Next, as shown in FIG. 7(B), the top of semiconductor wafer 11 is covered with a resin layer 13 so that electrodes 14 for external connection are lead out from the surface of resin layer 13. After that, semiconductor elements 12 are divided along dicing lines 15 of semiconductor wafer 11 so as to obtain a completed product, as shown in FIG. 7(C). Resin layer 13 only covers the top surfaces (in some cases the rear surfaces are also covered) of semiconductor elements 12 and silicon semiconductor substrates are exposed from the sidewalls of semiconductor elements 12. An electrode 14 is electrically connected to an integrated circuit network formed beneath resin layer 13. Thus, the mounting of this semiconductor device is implemented by oppositely adhering electrodes 14 to the conductive pattern formed on a substrate.
Such a semiconductor device has a package size that is equal to the chip size of a semiconductor element and can be oppositely adhered to a substrate and, therefore, there is an advantage wherein the area required for mounting can be greatly reduced. In addition, there is an advantage wherein the post-processing costs can be reduced. This structure is disclosed in, for example, Japanese Unexamined Patent Publication Hei-9-64049.
The semiconductor device according to the conventional art shown in FIG. 6 is connected to a conductive pattern on a substrate, for example, via lead terminals 3, while the semiconductor device shown in FIG. 7 according to the conventional art is connected to a conductive pattern on a substrate, for example, via electrodes 14, as described above. That is to say, lead terminals 3 or electrodes 14, respectively, are secured to a conductive pattern on a substrate via, for example, solder. At this time visual inspection of the solder after mounting can easily be carried out after the semiconductor device has been secured to a conductive pattern on a substrate in the case wherein the semiconductor device has a structure wherein lead terminals 3 are lead out to the outside of resin layer 2, as shown in FIG. 6. On the other hand, electrodes 14 are located on the surface of the semiconductor device in the case wherein the semiconductor device is of a CSP type, as shown in FIG. 7. Therefore, a problem arises wherein visual inspection of the mounted state of the solder is difficult to carry out because the solder after mounting is located on the rear surface of the microscopic semiconductor device after the semiconductor device is secured to a conductive pattern of a substrate.
In addition, the semiconductor device shown in FIG. 6 has a problem wherein there is a limit to the degree to which the area required for mounting the semiconductor device can be scaled down because of the protrusion of lead terminals 3 out of resin layer 2, as described above. Therefore, there is a problem in the semiconductor market at the present time such that there is a demand for a CSP-type semiconductor device wherein visual inspection of the mounted state of the solder after mounting of the semiconductor device can easily be carried out.